21 research outputs found

    Gray-code TDC with improved linearity and scalability for LiDAR applications

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    This paper presents a TDC architecture based on a gray code oscillator with improved linearity, for FPGA implementations. The proposed architecture introduces manual routing as a method to improve the TDC linearity and precision, by controlling the gray code oscillator Datapath, which also reduces the need for calibration mechanisms. Furthermore, the proposed manual routing procedure improves the performance homogeneity across multiple TDC channels, enabling the use of the same calibration module across multiple channels, if further improved precision is required. The proposed TDC channel uses only 16 FPGA logic resources (considering the Xilinx 7 series platform), making it suitable for applications where a large number of measurement channels are required. To validate the proposed architecture and routing procedure, two channels were integrated with a coarse counter, a FIFO memory and an AXI interface, to assemble the pulse measurement unit. A comparison between the default routing implementation and the proposed manual routing has been performed, shown an improvement of 27% on the overall TDC single-shot precision. The implemented TDC achieved a 380 ps RMS resolution, a maximum DNL of 0.38 LSB and a peak-to-peak INL of 0.69 LSB, corresponding to a 21.7% and 70.4% improvement, respectively, when compared to the default design approach.FCT - Fundação para a Ciência e a Tecnologia(037902

    All-digital time-to-digital converter design methodology based on structured data paths

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    Time-to-Digital Converters (TDC) are popular circuits in many applications, where high resolution time measurements are required, for example, in Positron Emission Tomography (PET). Besides its resolution, the TDC's linearity is also an important performance indicator, therefore calibration circuits usually play an important role on TDCs architectures. This paper presents an all-digital TDC implemented using Structured Datapath to reduce the need for calibration circuitry and cells custom design, without compromising the TDC's linearity. The proposed design is fully implementable using a Hardware Description Language (HDL) and enables a complete design flow automation, reducing both development time and system's complexity. The TDC is based on a Delay Locked Loop (DLL) paired with a coarse counter to increase measurement range. The proposed architecture and the design approach have proven to be efficient in developing a high resolution TDC with high linearity. The proposed TDC was implemented in TSMC 0.18 μm CMOS technology process achieving a resolution of 180ps, with Differential Non-Linearity (DNL) and Integral Non-Linearity (INL) under 0.6 LSB.FRCT - Fundo Regional para a Ciência e Tecnologia(PDE/BDE/114562/2016

    Technology independent ASIC based time to digital converter

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    This paper proposes a design methodology for a synthesizable, fully digital TDC architecture. The TDC was implemented using a hardware description language (HDL), which improves portability between platforms and technologies and significantly reduces design time. The proposed design flow is fully automated using TCL scripting and standard CAD tools configuration files. The TDC is based on a Tapped Delay Line architecture and explores the use of Structured Data Path (SDP) as a way to improve the TDL linearity by homogenizing the routing and parasitic capacitances across the multiple TDL’s steps. The studied approach also secures a stable, temperature independent measurement operation. The proposed TDC architecture was fabricated using TSMC 180nm CMOS process technology, with a 50MHz reference clock and a supply voltage of 1.8V. The fabricated TDC achieved an 111ps RMS resolution and a single-shot precision of 54ps (0.48 LSB) and 279ps (2.51 LSB), with and without post-measurement software calibration, respectively. The DNL across the channel is mostly under 0.3 LSB and a maximum of 8 LSB peak-to-peak INL was achieved, when no calibration is applied.- (037902

    Influence of mechanical stress in a packaged frequency-modulated MEMS accelerometer

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    Frequency modulated accelerometers composed of two double-ended tuning fork (DETF) resonators on a differential configuration were characterized for their sensitivity to force applied to their package. Commonly, differential architectures are employed to cancel common mode errors, such as the mechanical stress or temperature dependency. The device dependence to mechanical stress was experimentally measured for forces up to 15 N and a reduction of about 5.6 times was obtained on the differential measurement. Additionally, the silicon dies were glued to chip-carriers using two different glues with distinct properties, and their sensitivity to stress was compared. The effectiveness of a viscoelastic glue over an epoxy-based glue for stress decoupling was tested. Long-term measurements under constant force were experimentally performed and for a time period of approximately 100 min, the stress relaxation and creeping of the viscoelastic glue enabled the recovery to the initial output of the sensor.The first author is supported by FCT - Fundacao para a Ciencia e Tecnologia through the grant PDE/BDE/114564/2016. This work is supported by FCT with the reference project UID/EEA/04436/2019

    Auto-calibrated, thermal-compensated MEMS for smart inclinometers

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    Tese de Doutoramento - Programa Doutoral em Engenharia Electrónica e de Computadores (PDEEC) - Especialidade de Instrumentação e Microssistemas EletrónicosThe electronic control of a mechanical structure with micro dimensions, offers unique opportunities to exploit the tight coupling between co-integrated micromechanical structures and ICs (=Micro Electro Mechanical Systems (MEMS)). This coupling allows the implementation of integrated data-acquisition systems, with overall functionality or specifications that cannot be met using individually designed structures and circuits. This work focus on the development of a new class of MEMS-based inclinometers that includes electromechanical pre-processing of the mechanical signal in the mechanical domain and thermal compensation. The force-dependent pull-in voltage of a micromechanical structure, due to a sufficiently large electrostatic field, enables the realization of a high-resolution, low-bandwidth inclinometer. Pull-in is characterized by the sudden loss of stability in electrostatically actuated parallel-plate devices. Since pull-in voltage is stable and easy to measure, it enables an effective transduction mechanism that does not require complex readout electronics. A switched capacitor based complementary metal-oxide-semiconductor (CMOS) integrated circuit is developed, fabricated and used to detect the large capacitance change in the MEMS sensing element, while controlling a high-resolution external actuation system. Dedicated MEMS microstructures with extra proof mass show high sensitivity, 269mV/◦ with a non-linearity better than 0.5%FS (Full Scale of ±23◦). The measured noise is limited by the actuation system, rather than the mechanicalthermal white noise of the MEMS device, setting the sensor’s resolution at 75μ◦, high above state-of-the-art MEMS devices. The characteristics of this dedicated MEMS inclinometer system enables an thermal compensation mechanism, which increases the sensor stability to values better than 0.004%FS.O controlo eletrónico de estruturas mecânicas de micro dimensões, oferece oportunidades únicas para a exploração do acoplamento integrado entre microestruturas mecânicas e circuitos integrados (=Micro Electro Mechanical Systems MEMS). Este tipo de acoplamento permite a implementação de sistemas de aquisição de dados integrados, com funcionalidades ou especificações que não poderiam ser atingidas por estruturas ou circuitos desenhados individualmente. Este trabalho foca-se no desenvolvimento de um novo tipo de inclinómetros MEMS que inclui mecanismos de compensação térmica diretamente no domínio mecânico. A tensão de pull-in de uma microestrutura mecânica, possibilita a criação de inclinómetros de elevada resolução e baixa largura de banda. O fenómeno de pullin é caracterizado pela súbita perda de estabilidade em estruturas de elétrodosparalelos, quando electrostaticamente atuadas. Uma vez que a tensão de pull-in é estável e fácil de medir, é possível criar um método de transdução eficiente, sem ser necessário um front-end capacitivo de elevada complexidade. Um circuito integrado, baseado num amplificador de condensadores comutados, é desenvolvido, fabricado e usado para detetar a variação de capacidade no elemento sensorial, ao mesmo tempo que controla o sistema de atuação externo de elevada resolução. As microestruturas fabricadas com uma massa-inercial adicional, demonstraram elevada sensibilidade, 269mV/◦ (não linearidade < 0.5%, escala completa de ±23◦). O ruído medido não foi limitado pelo ruído termomecânico da estrutura, mas sim pelo sistema de atuação, colocando a resolução do sensor em 75μ◦, claramente acima do estado da arte em dispositivos MEMS. As características únicas deste inclinómetro, permitem a implementação de mecanismos de compensação térmica, podendo melhorar a estabilidade do sensor para valores superiores a 0.004%FS

    Recent developments and challenges in FPGA-Based time-to-digital converters

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    Over the past few years, the gap between field-programmable gate array (FPGA) and application-specific integrated circuit (ASIC) performance levels has been narrowed due to the constant development of FPGA technology. The high performance, together with the lower development costs and a shorter time to market, turns FPGA-based platforms attractive for a huge range of applications, among them time-To-digital converters (TDCs). It is, therefore, important to analyze the evolution of FPGA-based TDCs to better understand where the research efforts should be focused in the near future. This article presents and discusses the improvements on the FPGA-based TDC research, aiming to be a starting point for new studies on this field, with some guidelines for future research. A state-of-The-Art literature review on the FPGA-based TDC is presented, aiming to categorize and discuss the existing architectures. This discussion addresses architectures' characteristics, limitations, and areas of application.FRCT - Fundo Regional para a Ciência e Tecnologia(PDE/BDE/114562/2016

    Designing synchronizers for Nutt-TDCs

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    Applications requiring both high resolution time measurement and large dynamic range demand for the integration of high-performance Time-to-Digital Converters (TDCs) and coarse counting methods which operate asynchronously. When using two asynchronous counting methods, the use of a synchronization mechanism is mandatory to correct metastability errors. Moreover, the placement and routing tools are designed and optimized for synchronous designs, being asynchronous behaviour hard to constraint. Since TDC's principle of operation is based on the asynchronous characteristic of the pulse duration to be measured, this may lead to sub-optimal layouts. In this paper a design methodology for Nutt-TDC synchronizers is presented. The proposed methodology fully solves problems related with automatic placement and routing for proper synchronizer operation. A solution to reduce the critical signals' skew is also proposed along with guidelines on how to define the timing window at which the synchronization must be applied. To validate the proposed methodology a use case implementation of a Nutt-TDC based on a tapped delay line (TDL) is presented. The implemented synchronizer was able to eliminate the existing metastability and synchronization errors validating the efficacy of the proposed methodology.FCT - Fundação para a Ciência e a Tecnologia (PDE/BDE/114562/2016

    High-resolution MEMS inclinometer based on pull-in voltage

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    High-resolution pull-in-based microelectromechanical system (MEMS) inclinometers are presented in this paper. Pull-in is characterized by the sudden loss of stability in electrostatically actuated parallel-plate structures, and since pull-in voltage is stable and easy to measure, it enables an effective transduction mechanism that does not require complex and stable capacitive readout electronics. The MEMS devices used to test the novel architecture have differential actuation electrodes resulting in two pull-in voltages that change differentially with applied acceleration. Dedicated MEMS microstructures with extra proof mass show high sensitivity; 269 mV/degrees with a nonlinearity <0.5% FS (Full Scale of +/-23 degrees). The measured noise is limited by the actuation mechanism, setting the sensor's resolution at 75 mu degrees; high above state-of-the-art MEMS devices.The work of F.S. Alves was supported by the Portuguese Foundation for Science and Technology (FCT) under Grant SFRH/BD/90172/2012.info:eu-repo/semantics/publishedVersio

    High precision, geometry independent analytical method for self-inductance calculation in planar coils

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    This paper presents a versatile tool for the self-inductance calculation of planar coils. Due to the growing interest in planar coils in the past few years, the possibility of using an analytical model as a valid alternative to FEM simulations, regarding versatility and result reliability, would be of great interest. The ideal scenario would be to combine speed, precision, easy interaction and understanding, while adding versatility in terms of geometry. To achieve that, a tool, based on Grover equations, that calculates the self-inductance of planar coils with a general geometry has been developed. The results achieved using this method, considering different coil geometries and dimensions, were compared with the main analytical methods that can be found in the literature, proving the reliability of the proposed method. This model has the novelty of not having any limitation on the coil geometry or dimension, which is not the case for the other existing methods.This work has been supported by FCT – Fundação para a Ciência e Tecnologia with in the R&D Units Project Scope: UIDB/00319/2020 and European Structural and Investment Funds in the FEDER component, through the Operational Competitiveness and Internationalization Programme (COM-PETE 2020) [Project nº 037902; Funding Reference: POCI-01-0247-FEDER-037902]

    High-performance pull-in time accelerometer

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    A closed-loop accelerometer based on electrostatic pull-in time is presented here. The main goal is to achieve high-performance, namely in respect to noise and sensitivity, with a very simple readout mechanism. An integrated system was implemented comprising actuation and readout circuitry, FPGA and MEMS sensor. It presents a good performance in comparison to the state-of-the-art. Experimental measurements have shown a sensitivity of 61.3 V-2/g, dynamic range of 110 dB and a noise level set below 3 mu g/root Hz, by the mechanical-thermal noise only. The measured bias stability is better than +/- 250 mu g over 48h with temperature control of +/- 1 degrees C.Rosana Dias is supported by the NanoTRAINforGrowth COFUND Fellowship Program (project FP7-COF-NANOTRAIN, grant PCOFUND-GA2012-600375). Filipe Alves is supported by FCT, the Portuguese Foundation for Science and Technology (grant SFRH/BD/90172/2012).info:eu-repo/semantics/publishedVersio
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